1. Field of Invention
The present invention relates to a data recovery apparatus and method for reproducing recovery data, and more particularly, to a data recovery apparatus and method with three quarter steps oversampling.
2. Description of Related Art
Electronic circuits are developed towards operating at high-speed and miniaturization. It is a subject worth researching how to transmit data correctly at a high data transmissionrate. Take flat panel displays as an example, with increasing scale flat panel displays, the color intensity and resolution provided by the displays are also increased. The resolutions of SVGA (800×600 pixels) and XGA (1024×768 pixels) have become basic requirements for flat panel displays. The improvement of resolution means the increase of the amount and speed of data transmission. In particular, in the flat panel display system, the most obvious bottleneck encountered in the data transmission is an interface between a clock controller of the LCD and a display card directly connected thereto.
FIG. 1 shows a data transmission interface between the clock controller and the display card in a typical flat panel display. Referring to FIG. 1, the transmission terminal (i.e. display card 110) transmits image signals with 28 bits wide to the receiver (i.e. timing controller 140 in the flat panel display) through a low-voltage differential signaling (LVDS) interface. The LVDS interface comprises an LVDS transmitting unit 120 and an LVDS receiving unit 130. The LVDS transmitting unit 120 uses four multiplexers (MUX) to translate image signals with 28 bits wide output from the display card 110 to 4 bits wide and 7 bits deep LVDS data, and transmits the LVDS data to the LVDS receiving unit 130 in a differential signal form. In an LVDS interface standard, the transmitter 120 additionally transmits a set clock signal pair to the receiver through a phase lock loop PLL. Therefore, the data recovery circuit DRC of the receiver 130 can recover other data by using the clock, and tramslate the 4 bits wide data to a 28 bits wide data. FIG. 2A-2C shows the operation timing of three times oversampling. A conventional clock and data recovery circuits mainly employ a three times oversampling architecture to recover input data for preventing errors induced by skews between the clock and the data, thereby correctly recovering the data inputted.
FIG. 3 shows a conventional architecture of a clock and data recovery circuit in the receiver 130 of FIG. 1. Referring to FIG. 3 and FIG. 2A concurrently, the clock and data recovery circuit comprises input buffers 205 and 210, a data sampler 215, a phase lock loop 220, a synchronizer 225, a phase detector 230, a voter 235, a digital low-pass filter 240, and a phase selector 245. Firstly, the input buffers 205, 210 convert an input data streams Din+, Din− and input clocks CLKin+, CLKin− in the form of LVDS to a form of full swing signals, which is transmitted to the data sampler 215 and the phase lock loop 220 respectively. The phase lock loop 220 locks the full swing input clocks, and provides 21 sampling clocks with different phases to the data sampler 215. The data sampler 215 samples three times for each step of the bit signals d0-d6 and forms a 21 bits wide data stream because of utilizing 21 the sampling clocks with different phases. Then, the synchronizer 225 synchronizes the sampled data output from the data sampler 215.
By comparing the three sampled data in each step (e.g. d0 in FIG. 2A), the phase detector 230 can detect whether the input data stream leads or lags the input clocks. According to the detected result of the bit data d0-d6, the phase detector 230 outputs 7 set signal pairs (each of the signal pairs includes an “upper” bit and a “lower” bit) correspondingly. For example, when the phases of the sampling clocks lag the input data stream, as shown in FIG. 2B, the phase detector 230 detects that the third sampled result is different from the first and second sampled results in each step (e.g. d0) of the input data stream, and the phase detector 230 outputs an “upper” signal to the voter 235 in the corresponding signal pair. On the contrary, when the phases of the sampling clocks lead the input data stream, as shown in FIG. 2C, the phase detector 230 detects that the first sampled result is different from the second and third sampled results in each step (e.g. d0) of the input data stream, and the phase detector 230 outputs a “lower” signal to the voter 235 in the corresponding signal pair.
The voter 235 and the phase detector 230 output the “upper” and “lower” signals to the phase selector 245 in accordance with the number of the output “upper” signals and “lower” signals in the 7 set signal pairs. For example, in a clock period, if there are one “upper” signal and three “lower” signals in the 7 set signal pairs received by the voter 235, the voter 235 outputs the “lower” signals to the phase selector 245.
The digital low-pass filter 240 is used to filter noises to prevent a jitter effect from affecting the detected results. The phase selector 245 receives the the “upper” and “lower” signals output from the voter 235 through the digital low-pass filter 240. If the phase selector 245 receives the “upper” signals output from the voter 235, which means the phase selector 245 receives a detected result with an indicating of “the input data stream Din leads the input clock CLKin”, as shown in FIG. 2B, the phase selector 245 shifts the 21 sampled phases upwardly (left in the drawings) by one phase in the next clock period, as shown in FIG. 2A. In contrast, if the phase selector 245 receives the “lower” signals output from the voter 235, which means the phase selector 245 receives a detected result with an indicating of “the input data stream Din leads the input clock CLKin”, as shown in FIG. 2C, the phase selector 245 shifts the 21 sampled phases downwardly (right in the figures) by one phase in the next clock period, as shown in FIG. 2A. Finally, the synchronizer 225 recovers the received sampled data to be a recovery data Dout in accordance with the selection results of the phase selector 245.
In conventional technology, when the skew of input data is close to a half step, the three times oversampling architecture cannot distinguish whether the skew leads or lags the sampling clock, which may induce the errors in the recovery data. In addition, as the conventional phase selecting architecture is used with a three times oversampling architecture, 21 sampling clocks are needed in the LVDS receiver applications in flat panel display systems, therefore, the complexity of circuit layout is increased and the layout area is expanded as well.